Intel Shows Off Desktop Processor Using Next-Gen Architecture

Code-named Conroe, the processor will be a dual-core part made using Intel's 65-nanometer technology. Intel expects desktops based on the chip to show up in the third quarter, Pat Gelsinger, senior vice president of Intel's Digital Enterprise Group, said in a keynote speech at the Intel Developer Forum (IDF) in San Francisco.

Conroe was unveiled at the same time Intel formally gave some details about the Core Microarchitecture. Intel was widely expected to release more information about the architecture this week, and the chip giant used the keynote to hone in on ship dates for Core-based server and mobile products.

Though Intel has been talking about releasing the architecture since last year, some of its current products have taken a beating from Advanced Micro Devices in performance and power consumption, particularly the server chips. AMD more doubled its x86 server market share to 16 percent, according to Mercury Research, on the strength of its Opteron processor technology.

Intel's new architecture is designed to get performance gains by packing two CPUs running at lower clock speeds onto one die and increasing the number of tasks that can be run in parallel. By packing more cores on the die, Intel believes it can offer better performance and maintain efficient power consumption, Intel CTO Justin Rattner said. Boosting clock speed alone will exponentially increase power requirements, he said.

Intel also increased the number of instructions that can be executed in a single clock cycle from two to four. The company also developed a shared L2 cache on the chip, whereas previous Intel chips required a separate cache for each core. Sharing the cache means each CPU can take what it needs when it needs it, rather than being limited to a smaller, dedicated cache, Rattner said. That gives the processors an immediate pathway to share information.

Rattner said Intel improved the prefetch algorithms that anticipate which instructions to bring into the cache and advanced power gating that shuts down various portions of the chip logic that aren't needed for execution.

Intel's upcoming mobile chips based on this architecture will realize at least a 20 percent increase in performance while keeping energy and battery life constant, according to Rattner. He said desktop chips will see a more than 40 percent performance improvement and a 40 percent reduction in power requirements, and servers chips will get an 80 percent bump in performance with a 35 percent reduction in power.

Intel's server chips based on this architecture, code-named Woodcrest, are expected to ship to OEMs and system builders in the third quarter. The mobile chips, code-named Merom, are due to ship in the fourth quarter.

Though Intel’s next-gen architecture chips promise various benefits, their real-world performance won't be known until systems using the chips actually ship.

Envisioneering Group analyst Richard Doherty said Intel's move to combine cores with lower clock speeds is the best way to increase performance while reducing power, but for the parallelism benefits to be realized, software must support it effectively. The industry's shift to measure performance relative to power consumption also needs a unified measurement to fairly compare software and systems, he added. "It's going to take a while to get a metric for this," he said.

On the eve of IDF, Intel President and CEO Paul Otellini told CRN that the Conroe chip will ship with integrated management and hardware-assisted virtualization. Intel plans to position the chip as the basis for client systems that VARs and system builders can use to offer advanced managed services. The company’s current Active Management Technology includes the ability to remotely turn on a computer that had been previously powered off as well as collect data about computers that are off or not running because of system problems.

A expanded version of the technology, due out later this year but also expected in Conroe, will support the WS Management standard and a "circuit breaker" that will help stop denial-of-service attempts, Gelsinger said.

Intel also demonstrated servers running with its quad-core processors. Intel said these chips will ship in 2007 and be made using a 45-nanometer process. However, Rattner couldn’t specify a road map for chips with more than four cores but said more information on the company’s plans in 2008 and beyond would start to appear at the fall IDF. Intel this week announced a research plan to investigate combining 10 or more cores in one die.