Tilera, Quanta Collaborate On Dense Servers For Cloud, Services Apps


Processor startup Tilera and Quanta Computer have collaborated to build what they bill as the world's highest compute density server, a unit which fits up to 10,000 processor cores on a standard rack and is aimed at cloud computing and service providers.

Tilera, which was founded in 2004 as a fabless semiconductor maker, unveiled its first product, a 16-core processor in 2007, and followed that up last year with its GX family of 16-core to 100-core processors, said Troy Bailey, vice president of marketing for the San Jose, Calif.-based company.

Quanta, which along with Broadcom is a strategic investor in Tilera, this week unveiled the S2Q server.

The S2Q fits eight processor nodes into a 2U rack-mount enclosure. Each node contains a 64-core TilePro64 processor, giving 512 cores per 2U of space. The nodes also include 176 Gbits per second of I/O bandwidth, up to 64 DIMM memory slots, and up to 24 2.5-inch hot-plug SAS, SATA, or solid-state drives.

Each node consumes between 35 Watts and 50 watts of power, which means that a full rack of S2Q nodes with up to 10,000 cores consumes about 8 KW of power.

The company's Tile family of processors were designed purely for performance, and have few of the more advanced features of AMD and Intel processors, Bailey said.

"Our main difference is in how we designed the cores and connect them together," he said. "A lot of companies that implement multi-core technology are seeing a decline in incremental performance, because they get a lot of bottlenecks when communicating with other devices."

Tilera, on the other hand, uses a mesh configuration under which the cores are arranged in an eight-by-eight grid, which means the bus lines between the cores are very short and switched at the processor's clock frequency, Bailey said.

"We can go to 1,000 cores without running into scalability issues," he said.

Tilera's processors have a different architecture from the industry-standard x86 processors from Intel and AMD. However, Bailey said, they can be programmed using C and C++ using standard compilers, although applications written for the Tile processors are not binary-compatible with applications for other processors.

 

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