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The writing was on the power wall before Tejas lost its statehood, and chip makers were seeking ways to improve processing throughput that wasn't tied to increases in clock speed, or power consumption. By 1995, Intel's Pentium Pro processor was marketed with features such as an execution pipeline, out-of-order instruction processing, second-level cache and other techniques to give program execution a boost. This was a predecessor to the dual-core Pentium II and Xeon processors.
As Intel's troubled Pentium processor so clearly illustrated, the laws of nature and diminishing returns were catching up to the Law of Moore. The complex logic required to implement execution pipelines and other throughput techniques required lots of expensive silicon real estate and were highly prone to post-manufacture errors, according to the SciDAC report.
It was clear to chip makers that it was becoming exceedingly impractical (and sometimes impossible) to verify all that complex logic; the cost of these designs was reaching into the hundreds of millions of dollars, the report stated. "The likelihood of chip defects will continue to increase, and any defect makes the core that contains it non-functional." Manufacturers were seeing that the larger and more complex a chip's design, the lower its yield would be.
The SciDAC report cited "A View of the Parallel Computing Landscape,” a paper published in 2006 by a team of computer scientists from Lawrence Berkeley National Laboratory (LBNL) and the University of California (UC), Berkeley. The Berkeley scientists offered the following solutions for these processor issues:
Power: Parallelism is an energy-efficient way to achieve performance. Many simple cores offer higher performance per unit area for parallel codes than a comparable design employing smaller numbers of complex cores.
Design Cost: The behavior of a smaller, simpler processing element is much easier to predict within existing electronic design-automation workflows and more amenable to formal verification. Lower complexity makes the chip more economical to design and produce.
Defect Tolerance: Smaller processing elements provide an economical way to improve defect tolerance by providing many redundant cores that can be turned off if there are defects.
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