Dual-Core Servers: AMD or Intel?

Main memory is another area where Intel departs from AMD in terms of architectural design. While both chipmakers use DDR2 RAM chips, this is where the similarity in their memory subsystems ends.

AMD integrates the memory controller directly onto the processor chip. The chip, in turn, directly connects its 240 or so parallel circuit traces to the memory array on the motherboard. The maximum memory allowed by the system increases in linear fashion with the number of processor chips in the system.

Also, the AMD processor makes use of industry-standard registered ECC DDR2 RAM modules. This helps limit system costs, even when large amounts of memory are used.

Intel does not integrate the Xeon's memory controller directly onto the chip -- memory transactions are routed through the FSB. So Intel had to come up with a new way of doing things, to keep pace with system demands on memory bandwidth. Intel's solution is called Fully Buffered DIMM (FB-DIMM), which also uses DDR2 RAM chips on the modules.

Under Intel's arrangement, part of the memory controller is integrated onto the DIMM itself; it is called the Advanced Memory Buffer (AMB). Each FB-DIMM has an AMB chip, in addition to the actual DDR2 RAM chips. Only the common clock signal source and a serial link to the AMB chips are located on the Intel's Northbridge chip (part of the motherboard chipset, which I discuss below). This point-to-point serial connection requires only 69 circuit traces per memory channel, compared with the 240 circuit traces of AMD's parallel interface.

Each of Intel's FB-DIMMs uses more power than do the standard registered modules used in AMD systems, mainly due to their AMB chip. Consequently, the Intel units also generate more heat.

One advantage of Intel's split controller design: It introduces Error Checking and Correction (ECC) schemes to the address and control signals, in addition to the data signals. This increases system stability at high clock speeds.

Also, Intel's design scales well, in terms of available bandwidth and maximum memory capacity. But the full potential of this new design has not yet been realized with existing components now available to system builders.