Patla recently replaced former server chief Randy Allen, who was promoted in May to head up AMD's Computing Solutions Group in a major executive reshuffle that presaged Dirk Meyer's replacement of Hector Ruiz as CEO in July.
AMD's quad-core Shanghai processors are achieving 35 percent increases in both power efficiency and performance in clock-for-clock competition over the chip maker's current 65nm generation of quad-core server chips formerly code named Barcelona, Patla said in a press briefing held Tuesday in San Francisco.
The server chief said AMD had reviewed its engineering processes ahead of the Shanghai validation process in an effort to avoid silicon glitches like the TLB errata that slowed the ramp of its Barcelona and Phenom chips in the first half of 2008.
"Picking up from Barcelona's launch, internally, starting back in January, we really took a look from an engineering perspective at how do we learn from the Barcelona missteps and really instill confidence in Shanghai, our 45nm product," Patla said.
"AMD grew really quickly over the last couple of years and so did the complexities of our products, so we had to make sure our processes were scaling with the products we were bringing to market."
The chip maker slowed down the initial tape-outs of Shanghai silicon and spent more time on testing and the validation process for the chips, he said. But by working on validation with Tier 1 OEM partners, AMD was actually able to move up its shipment schedule from Q1 of 2009 to Q4 of 2008 for its first 45nm processors, Patla added.
AMD's main rival, microprocessor market leader Intel of Santa Clara, Calif., began shipping its first 45nm parts in the second half of 2007. Intel's next fabrication process shift will be to 32nm, with production scheduled for late 2009 or early 2010. The chip leader is also planning its own major product ramp around its new Core i7, or Nehalem microarchitecture in roughly the same timeframe as AMD's Shanghai roll-out.
Next: More Roadmap News From AMD
