Intel Details Future Interconnect, Instruction Set Plans
At the Intel Developer Forum, Pat Gelsinger, Intel senior vice president and general manager of the Digital Enterprise group, said the Santa Clara, Calif. chipmaker is busy developing new instruction sets and advancing its management and interconnect technologies to help accelerate application and Web service execution in the data center.
Recently, Intel has announced its Core 2 Duo and Core 2 Quad processors as a way to elevate processing power. But customers need complementary bumps in memory and I/O technologies with the advent of those processors, 3-D, graphically intensive applications Windows Vista, high-definition video on the Web and Web services like Google and Yahoo, he said.
The "Geneseo" project, a joint effort by Intel and IBM, is one such effort. The proposed extensions to the PCI Express I/O interconnect specification which aims to include co-located hardware on the bus are designed to be more efficient than add-in cards or other software approaches, Intel said.
At IDF, several vendors announced support for Geneseo, among them Adaptec, Altera, Broadcom, ClearSpeed, Emulex, LSI Logic, QLogic, Synposis, Tektronics and Xilinx.
Gelsinger said he cannot provide a timeline for Geneseo, but he anticipated the specification would gain approval sometime next year and said it was reasonable to infer that products based on the extended PCIe will follow in 2008. PCI Express 2.0 is due early next year.
Sun stopped short of saying it would integrate Geneseo in its products, but praised the new application accelerator interconnect.
"We think it's a good idea," said Andy Bechtolshein, co-founder and vice president of architecture at Sun. "It's a universal standard and this extension is the evolution of PCI Express. The enhancement is useful for accelerators. "
AMD has its own Direct Connect Architecture and this week announced its Torrenza platform to enable processor socket compatibility.
When asked how the Geneseo application accelerator technology is different from AMD's Torrenza, Gelsinger said Geneseo is based on an industry standard specification and a "standard acceleration architecture versus a narrow fixed function accelerator inside a proprietary platform," he said. "We're not talking about the same thing whatsoever."
In addition to the I/O technology, Intel announced it would license its front side bus (FSB) technology to Xilinx and Altera and also plans to develop new instruction sets for the company's processors to support many graphic intensive applications and platforms, including video encoding and processing, 3-D imaging , gaming, Web servers and application servers.
The 50 new SSE 4 instructions under development will extend the Intel 64 instruction set architecture to optimize for Intel's 45 nanometer silicon manufacturing process. New Intel products using the extensions will roll out over the next two years, Gelsinger said.
Finally, Intel vPro, which was launched earlier this month, will also be updated in 2007 with new Intel hardware security known as Trusted Execution Technology (formerly code-named la Grande), additional deployment options and support for the Web services management specification, Intel said. vPro will also be incorporated into Intel's Centrino mobile processors next year.