80-Core Processor On Horizon At Intel
Intel (Santa Clara, Calif.) also tipped an SRAM and a silicon laser chip, as part of its ongoing research into terascale technology. Earlier this year, the company disclosed details about its internal terascale research program that promises to usher in the next wave of computing.
Terascale scaling and computing will be required in the future, said Justin Rattner, Intel Senior Fellow and chief technology officer. During the next decade, mega data centers will host more than a million servers, allowing end-users to access personal data, play photo-realistic games, share real-time video and do multimedia data mining, Rattner said at the Intel Developer Forum (IDF) in San Francisco.
This new usage model will challenge the industry to deliver high-speed computing performance and terabytes of bandwidth.
One of the first prototypes chips in Intel's program is the Tflops processor. Containing 80 simple cores and operating at 3.1 GHz, the goal of this experimental chip is to test interconnect strategies for moving terabytes of data from core to core and between cores and memory, according to Intel.
Unlike existing chip designs where hundreds of millions of transistors are arranged, this chip's design consists of 80 tiles laid out in an 8- by 10-block array, according to Intel.
Each tile includes a small core, or compute element, with a simple instruction set for processing floating-point data, but the silicon is not Intel x86-based processor compatible. The tile also includes a router connecting the core to an on-chip network that links all the cores to each other and gives them access to memory.
The second major part is a 20-Mbyte SRAM memory chip that is stacked on and bonded to the processor die. Stacking the die makes possible thousands of interconnects and provides more than a terabyte-per-second of bandwidth between memory and the cores, according to Intel.
The third product is the recently announced hybrid silicon laser chip developed in collaboration with researchers at University of California at Santa Barbara. This could lead to a terabit-per-second optical link capable of speeding terabytes of data between chips inside computers, between PCs and between servers inside data centers.
"When combined with our recent breakthroughs in silicon photonics, these experimental chips address the three major requirements for terascale computing—Tflops of performance, terabytes-per-second of memory bandwidth, and terabits-per-second of I/O capacity," Rattner said in a statement. "While any commercial application of these technologies is years away, it is an exciting first step in bringing tera-scale performance to PCs and servers."