Intel Updates Chip, Platform, Chipset Road Map


This quarter, the Santa Clara, Calif. chip giant plans to launch its much-anticipated "Santa Rosa" Centrino mobile platform and extend its mobile technology to smaller, more power-efficient PCs. The "Santa Rosa on Desktop" processors, for instance, will provide integrated 802.11n wireless support and optional Intel Turbo Memory for application acceleration.

Also this quarter, Intel plans to ship the Intel Series 3 chipset, an enhanced desktop chipset code-named Bear Lake, that will power Windows Vista and the Intel Viiv entertainment PC platform.

Intel 3 Series chipsets will provide improved graphics support in the form of Intel Clear Video technology and hardware support for Microsoft's DirectX10 for high-definition playback and 3-D visuals, Intel said. The chipsets also offer a boost in performance via their faster 1.333MHz front-side bus, support for DDR3 memory, PCI Express 2.0 and Intel Turbo Memory for accelerating application performance.

The chipset will be used in Intel's next-generation vPro processor technology, code-named Weybridge, in the second half of 2007 and in the Viiv platform later this year.

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At the Intel Developer Forum in Beijing, Intel said it's making steady progress on its first set of desktop and server chips developed with its 45nm Hi-K gate process technology.

Based on a preliminary 45nm quad-core desktop processor operating at 3.33 GHz, customers will enjoy a 15 percent improvement for imaging applications, a 25 percent improvement for 3-D rendering applications (such as Windows Vista) and a more than 40 percent boost for gaming and video encoding applications, according to Intel.

Intel's first set of "Penryn" Xeon server processors, also based on the 45nm Hi-K technology and due to begin shipping in 2007, are aimed at high-performance computing and workstation applications. According to Intel, the new Xeons will deliver a 45 percent increase in performance for high-bandwidth applications and a 25 percent boost for Java-based servers.

The next-gen "Nehalem" processor family will begin shipping in 2008 and offer one to eight cores per chip, as well as options such as system interconnects, integrated memory controllers and an integrated graphics engine.

On the high end, Intel detailed plans for the Xeon 7300 series of multiprocessors for MP Servers, code-named Caneland. Due for delivery in the third quarter, the Xeon 7300 quad-core and dual-core processors will be available in 80-watt and 50-watt versions for blade servers. The line will complete Xeon's transition to Intel's Core microarchitecture.

In addition, Intel said it plans to develop teraflop products based on its Project Larrabee platform, a highly parallel IA-based architecture that's easily programmable and will scale to trillions of floating point operations (teraflops) per second. As part of Larrabee, Intel will incorporate enhancements to accelerate the performance of scientific, data mining, visualization, analytics and other highly computing-intensive applications.