Intel Labs Unveils 48-Core Chip

"With a chip like this, you could imagine a cloud data center of the future which will be an order of magnitude more energy efficient than what exists today," said Justin Rattner, Intel's CTO and head of Intel Labs.

The prototype single-chip cloud computer, which Santa Clara, Calif.-based Intel has dubbed an SCC, is the second generation of Polaris, a many-core computer chip that Intel introduced at the International Solid State Circuit Conference (ISSCC) two years ago. The experimental 48-core chip shares some attributes of Intel's future-generation GPU microarchitecture, code named Larrabee, Rattner said.

As with Larrabee and unlike the first Polaris chip, the cores that make up Intel's new SCC are compatible with the x86 instruction set, or as Intel prefers it to be known, the Intel Architecture (IA).

The experimental 48-core computer chip "rethinks many of the approaches used in today's designs for laptops, PCs and servers," according Intel. One key such "rethinking" is the utilization of software to manage page-level memory coherency, rather than baking that functionality into the silicon as with previous architectures, Rattner said.

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Removing such hardware functionality is a silicon space-saver, allowing room for a new, high-speed on-chip information sharing network built onto the processor die. The SCC team also developed new power management techniques that Rattner said allow all 48 cores to operate while drawing as little as 25 watts in power. At peak performance, the prototype chip draws 125 watts, putting it within the power band of Intel's Core 2 and Nehalem-based processors currently on the market.

Intel will be sharing about 100 of the experimental chips with industry and academic partners in 2010, Rattner said. Research teams at Microsoft, ETH Zurich, University of California at Berkeley and the University of Illinois already have such chips to play with, he added.

"This is not a product. It never will be a product. But it provides a very good platform for conducting research," Rattner said.

Intel sees a strong play for future many-core chips in cloud computing installations, where energy efficiency and the ability to build extremely dense computing are at a premium. The "many-core era" will also mark a shift to computing that is more "immersive, social and perceptive," Rattner said.

"Computers will see and hear and they will probably speak, and do a number of other things that resemble what humans do," he said.

The experimental SCC was produced by 40 Intel Labs researchers in the U.S., Europe and India, Rattner said. The 1.3-billion transistor chip features Intel's current-generation 45-nanometer, high-k metal gate process technology. Bringing more cores, better power management and x86 compatibility to the first Polaris design was a largely glitch-free exercise, Rattner added.

"There was only one significant bug" during the design process, he said.

The chip's 48 x86-compatible cores are "the most ever built on a single chip," according to Intel. Those cores are laid out on the processor in a two-dimensional grid which further maps 24 tiles that have two cores apiece.

Rattner described the power management capabilities as "fine-grain," though not so fine-grain as to allow for power to be throttled up or down at the core level. Instead, it's possible to run each two-core tile at a different frequency, while the chip's regions -- six banks of four tiles -- can each be run at different voltages, Rattner said.

The second-generation 2D mesh network on the SCC features 24 routers, one per tile, and consumes just a third of the power of the previous Polaris network, Rattner said. Each core has its own dedicated L2 cache, with 256 Gbps bisection bandwidth and 64 Gbps duplex link bandwidth. The chip has four integrated, 64GB-addressable DDR3 memory controllers.