Intel to Introduce Sandy Bridge at IDF 2010
Forum architecture software CPU
Intel partners are particularly interested in the power efficiency gains that Sandy Bridge promises to bring. "There are sure to be some advantages in terms of energy savings, and it's exciting to watch devices becoming more powerful and more portable," said Todd Swank, vice president of marketing at system builder Nor-Tech, Burnsville, Minn.
Some Intel partners are more enamored with Sandy Bridge's potential to improve the performance of traditional desktops, given that no one knows exactly where Intel is headed in its new-found mobility and graphics card undertakings.
"Sandy Bridge will be Intel’s first product with respectable integrated graphics that could threaten the entry level discrete market," said Andy Kretzer, director of sales and marketing at Bold Data Technology, a Fremont, Calif.-based system builder.
While the integration of GPU and CPU functions on a single chip will have beneficial effects on performance, it could also have some economic consequences on the PC industry as a whole. For example, the graphical advancements coming in Sandy Bridge could have a negative impact on shipments of discrete graphics cards.
Some Intel partners see the GPU-CPU integration as a potential disadvantage for system builders. "It's already difficult to compete with less expensive technologies and jobs moving overseas. Unless it provides new opportunities in customization, which it might, more integration is not necessarily a good thing for the channel," said Swank.
But whether system builders like it not, this integration represents the future direction for all chipmakers. On Monday, while Intel is showcasing Sandy Bridge at IDF in San Francisco, rival AMD will be offering a glimpse of its forthcoming integrated chip architecture, code named Zacate.
Intel and AMD often try to take some wind out of each other's product announcements, and we're about to see the next chapter of this battle unfold around the CPU-GPU integration in both companies' chip architectures.