Samsung, Cadence Design Systems Build 32-nm SoC For Ambarella HD Camera

Samsung’s foundry business has already initiated production of the Ambarella A7L SoC, which was built using its gate-first, high-K metal gate (HKMG) processing technology. The 32-nm SoC leverages a complete Cadence design flow, including an Encounter digital implementation platform and an Incisive verification platform for IP integration and verification, along with an ARM Cortex processor.

"Teaming with Samsung Foundry and Cadence reduced our risk and gave us access to the most advanced foundry silicon process, superior IP and design methodology in addition to excellent design services," said Chan Lee, vice president of VLSI at Ambarella, in a statement. "Impressively, Samsung Foundry's process technology, combined with the Cadence digital flow, enabled us to hit our aggressive performance targets while achieving 95 percent power savings during power shutoff mode and 60 percent average power savings over operation and sleep modes."

Perhaps more intriguing than the 32-nm SoC itself was the wholly collaborative design approach behind it. Chi-Ping Hsu, senior vice president of research and development at Cadence's Silicon Realization Group, commented on the rarity of this sort of collaboration, and the benefit it presents for startup organizations like Ambarella, that may not have wide access to resources.

"The successful production tapeout of this Ambarella A7L design also demonstrates the synergy created when leading technology companies join forces throughout the design process," Hsu said in a statement, "and how companies like Ambarella are benefitting from such deep collaboration."

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