HP CTO Lays Out HP's Vision For Future Computer Architecture

Printer-friendly version Email this CRN article

It is also time to start moving away from the traditional storage hierarchy based on on-chip cache, main memory and mass storage. "Eighty percent, give or take, of what that computer is doing is actually moving data back and forth through this chain," Fink said.

While HP recently introduced a flash-optimized version of its 3PAR storage solution, HP and its peers need to take storage technology to new levels to meet future demands for high scalability and low power consumption, Fink said.

Traditional computer DRAM and flash memory are getting more and more dense, but the industry is approaching the point at which it will be hard to tell if a particular bit is a zero or a one. The industry, Fink said, is responding with three new memory technologies.

The first is spin transfer torque, which Fink said can be thought of as a bar magnet that represents a "1" when spun one way and represents a "0" when spun the other way, with the flipping done by a pulse current. It has high performance but a density lower than that of DRAM.

The second is phase change memory, or PCRAM. Phase change works by heating up a material that becomes a glass when cooled quickly and a crystal when cooled slowly. It has some of the properties of flash, but it has performance that, in some cases, can be worse that flash, he said.

The third is memristor, which works by changing the resistance of the right material from 0 ohms to 25,000 ohms by moving the material the distance of only 1 nanometer.

"The cool thing about this is that we can actually scale this tremendously," Fink said. "So we can achieve levels of scale that are much more significant than we can reach with flash or DRAM. It is persistent, a non-volatile memory. And we can have a line of site to performance that reaches the level of DRAM."

Fink showed a wafer that he said is expected to offer an estimated memory capacity of about 60 TB. Within another two years or so, that wafer will have a capacity of about 1.5 PB, all without the need for energy to retain the memory states.

NEXT: Wrapping Up The Future Of Computing

Printer-friendly version Email this CRN article