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Intel Looks Beyond Quad Core

Forget about quad core. Intel is already exploring ways to pack 10 to 100 cores on one die.

Though such products aren't expected until late in this decade, solution providers will find that the changes will impact the way they approach transactional solutions and custom applications.

Intel CTO Justin Rattner, at the start of the Intel Developer Conference held this week in San Francisco, told a group of journalists that Intel has initiated a formal research program aimed at bringing the next-generation of multicore processors to market. Called the TeraScale program, it will be a global effort involving more than 80 related projects, he said.

Processors with bundles of cores can mean a leap forward in the kind of computing that is available, Rattner said. Among the advances he expects: more intuitive interfaces, better simulations, virtual-reality gaming, and mining unstructured data.

"The future is characterized by terabytes of data and teraflops of computing power," he said.

To get there, however, Intel has to do more than develop a chip architecture that can support 10 or more cores, Rattner said. Platforms that support the chips must change as well as the software that will run on them.

One of the biggest roadblocks is developing software that has the kind of multithreaded support necessary for so many cores.

"There are applications that no one thought would scale beyond a couple of threads that will be looking at a good 32 threads," he said.

While there are parallelism solutions today that can handle multicore processing, when the industry reaches 10 or more cores software will need to be refined, he said.

This is particularly important for applications that access and manipulate transactional data because snags in parallelism can cause the wrong data returned, he said.

The main problem centers around multiple threads trying to access the same memory location at the same time and the way current software resolves these issues. Today's method is to employ "locks" that mange the order of important data as it makes its way in and out of memory. This has been the basis for parallel computing for decades, said Rattner.

Intel's proposal is adding something called transactional memory, he said. The solution would combine hardware and software that would be able to recognize when there is a conflict in the multiple threads running and would force all but one of those to back out of memory and try again.

Rattner said Intel has tweaked Java programming language to support this method as a proof of concept.

Along with these changes, Intel will be working on ways to increase bandwidth, I/O and memory. Power management -- an area where Intel has been taking hits over the past couple of years -- is also on the fore.

Raj Yavatkar, director of Intel's System Technology Lab, said Intel is working on what it calls the Energy Efficient System Architecture to help ensure the more powerful systems of tomorrow won't generate an electrical bill that will bankrupt a typical business.

Among the research projects under way are finding ways to get a system monitor to refresh itself when there aren't changes to the screen, improving blade cooling, and improving power management utilities.

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