IBM Unveils New Chip Technology That Breaks The 1 Nanometer Barrier

IBM’s “nanostack” semiconductor architecture, which can pack nearly 1 billion transistors onto a single chip, offers performance and energy efficiency gains that could prove crucial as AI computing becomes increasingly widespread. VARs and system integrators could tap into the technology.

IBM has developed the industry’s first sub-1 nanometer semiconductor technology that can pack nearly 100 billion transistors onto a single chip the size of a fingernail, the company said Thursday.

IBM said its new “nanostack” three-dimensional chip architecture, which can produce semiconductors at the 0.7 nm or 7 angstrom node technology level, marks a breakthrough for the semiconductor industry that has wrestled with the physical limits of traditional chip scaling as chip features approach atomic dimensions.

Semiconductors developed using the nanostack technology will provide up to a 50 percent gain in performance while offering 70 percent greater energy efficiency, IBM said—significant improvements at a time when the exploding use of AI technology is putting huge demands on IT hardware and data centers.

“What we’re announcing is not just an incremental step, it’s a meaningful leap forward, enabling up to 50 percent higher performance or 70 percent greater efficiency, and pointing to a future where the computing becomes significantly more powerful without a corresponding increase in energy [usage],” said Jay Gambetta, director of IBM Research, in a press briefing prior to today’s announcement.

“All this matters because semiconductors are the foundation of modern life, powering everything from AI systems to cloud infrastructure to the devices, networks, and critical systems that society and business depend on every day,” Gambetta said.

“Think about AI computing. Everyone demands more performance, but no one wants to pay the bill for the power, for all the electricity” AI systems use, said Huiming Bu, IBM vice president of global semiconductor R&D, also during the press briefing.

Don’t expect semiconductors using the new technology to begin hitting the market any time soon, however. IBM, in the nanostack press announcement, said its “expectation of the earliest adoption” of the new architecture forecasts the production of sub-1 nm chips “in as early as the next five years.” IBM said its semiconductor roadmap for nanostack “projects at least a decade of future scaling.”

Chip designers and manufacturers will be the earliest beneficiaries once the nanostack architecture moves from R&D to more widespread manufacturing adoption. System and hardware manufacturers will benefit by offering higher performing, more energy efficient products while software developers can develop applications that leverage those capabilities.

Ultimately the channel, including VARs and system integrators, can deliver more powerful, more efficient and more scalable solutions—including those incorporating AI—at a time when demands for processing power are growing exponentially.

Technology Breakthrough

With nanostack, semiconductor logic technology can extend for the first time below the nanometer node level and move toward angstrom-level scaling “where dimensions approach the size of individual atoms,” according to the IBM announcement.

The nanostack technology builds on the company’s current “nanosheet” chip architecture that debuted in 2021 and is widely used to produce 2 nm semiconductors.

Nanostack can produce chips with nearly twice the transistor density of 2 nm chips through the use of what IBM described as “a series of structural and material innovations.”

The primary development with nanostack is what IBM described as its “groundbreaking” 3-D architecture that “vertically stacks and staggers transistors,” according to the company’s description of the new technology, leveraging 3-D “sequential integration” to pack more transistors onto a chip.

“For the first time in our industry we are able to stack and stagger transistors in a vertical direction,” Bu said, describing nanostack as a new “inflection point” in semiconductor technology.

The new chip design also utilizes different material combinations within each stacked layer, which IBM said optimizes the performance and power efficiency of each transistor independent of each other.

Potential Broad Applicability

Bu said nanostack isn’t just a single innovation. “It is actually a device platform that can actually enable the future of [semiconductor] scaling for another decade beyond nanosheet,” he said.

Bu described nanostack as “a generic technology” that can be applied to many types of chips including CPUs, GPUs, mobile chips and more.

IBM said the nanostack architecture has been “experimentally validated” with results that confirm the nanostack technology can be physically built and supports “real computation.” The experiments included ultra-thin dielectric bonding in CMOS integration, demonstration of dual-channel engineering capability, and functional CMOS inverter operation with expected switching performance, according to the company announcement.

IBM said that in a presentation at last week’s VLSI 2026 Symposium IBM researchers demonstrated that the nanostack architecture provides 40 percent scaling in SRAM (static random access memory), which the company said helps chip designers create more efficient semiconductors while also supporting the high-bandwidth data demands of advanced AI workloads.

In terms of nanostack manufacturing, including relationships IBM has with foundries such as Japanese manufacturer Rapidus, Gambetta said IBM remains focused on its 2 nm chip technology for the time being and is not yet considering the details about “how we want to industrialize” the nanostack architecture.