Intel Heralds New Era With Alder Lake Hybrid CPU Architecture
For Alder Lake, Intel is relying on what it says are two new groundbreaking x86 CPU microarchitectures — an Efficiency core and a Performance core — and it will use an intelligent scheduler to tell the upcoming Windows 11 operating system when to shift workloads between the two core types to maximize performance and efficiency for desktops and laptops. ‘This is where the dynamic nature of our innovation shines,’ an Intel senior engineer says.
Intel is heralding a new era of computing with an upcoming hybrid CPU design that will combine two x86 microarchitectures to maximize performance and efficiency for desktop PCs and laptops.
As part of the Intel Architecture Day 2021 event this week, the Santa Clara, Calif.-based company on Thursday revealed several new details for its next generation of Intel Core processors, code-named Alder Lake, which will bring a significant change in how applications are assigned to the CPU’s cores when the first processors come out for desktops later this year.
Raja Koduri, head of Intel’s new Accelerated Computing Systems and Graphics Group, likened Alder Lake’s hybrid design to Formula One racing cars that “use hybrid technology to achieve maximum performance.”
“In addition to the conventional turbocharged engines that give them top speed and enough range to make it to the finish line on a tank of fuel, their electric power to blast them out of the corners with acceleration cannot be achieved with conventional engines,” he said in a pre-briefing with journalists.
For Alder Lake, Intel is relying on what it said are two new groundbreaking x86 CPU microarchitectures: the Efficient core, which will deliver major advances in performance and efficiency for client CPUs over Intel’s Skylake core that is used in several recent CPU generations, and the Performance core, which will provide advances in general-purpose compute and accelerated compute for client and data center CPUs.
The Efficient core, previously code-named Gracemont, is designed for efficient throughput with the goal of delivering “scalable multi-threaded performance for modern multi-tasking.” Compared to two Skylake cores running four threads, four Efficient cores can provide 80 percent more throughput performance while consuming less power and conversely perform the same level of throughput at 80 percent less power. For single-threaded performance, the Efficient core is 40 percent faster at the same power as Skylake while consuming 40 percent less power at the same performance level.
“What makes all this truly incredible is when you consider that we can deliver four of our new cores in a similar footprint as a single Skylake core,” said Stephen Robinson, chief architect for the Efficient core.
The Performance core, previously code-named Golden Cove, is considered the “highest performing CPU core Intel has ever built while also delivering a “step function in CPU architecture that will drive the next decade of compute,” according to Adi Yoaz, chief architect for the Performance core. Compared to the Cypress Cove core that powered 11th-generation Intel Core CPUs, the Performance core can provide an average improvement of 19 percent across a wide range of workloads.
Yoaz said the performance improvements are greater when considering applications that can take advantage of the Performance Core’s new instruction sets like Intel Advanced Matrix Extensions, or AMX, which represents the next generation of Intel’s built-in AI acceleration for machine learning inference and training in the data center, also known as Intel DL Boost.
With INT8 compute, for instance, AMX allows the Performance core to perform eight times more operations per cycle per core than Vector Neural Network Instructions, a previous generation of Intel DL Boost used in the previous generation of CPUs.
The Alder Lake architecture will combine the Efficient and Performance cores into a hybrid CPU that will sport up to 16 cores total, split evenly between Efficient and Performance cores. With Performance cores supporting two threads and Efficient cores supporting one, that will amount to 24 threads total.
Alder Lake processors will scale from “the highest-performance enthusiast desktops to the thinnest, most responsive Evo laptops,” and they will be built using the Intel 7 process technology, previously known as the company’s 10nm Enhanced SuperFin, according to Arik Gihon, chief architect for Alder Lake. The CPUs will also usher in support for two new standards — DDR5 memory and PCIe 5.0 connectivity — while also supporting Thunderbolt 4 and Wi-Fi 6E.
“One of our most important goals when designing Alder Lake was to support all client segments through a single highly scalable SoC architecture,” Gihon said.
Because Alder Lake will mark Intel’s first mainstream CPU architecture to come with two different kinds of cores, the company has created a new intelligent workload scheduler baked into the hardware called Intel Thread Director, which will know when to run applications on Performance cores and when to run them on Efficient cores in Microsoft’s upcoming Windows 11 operating system. The goal is to maximize the performance and efficiency of Alder Lake CPUs.
“The biggest challenge, the magic is to bring these two cores together, working efficiently with existing software,” Koduri said.
Rajshree Chabukswar, a senior principal engineer, called Intel Thread Director “one of the most significant and exciting innovations” in the company’s client CPU roadmap and said it goes beyond the conventional approach of “simply assigning threads to cores based on static rules,” which “leaves a lot of performance on the table and creates overhead with software development.”
“Thread Director technology allows us to provide smarter assistance to the OS by monitoring instruction mix, current state of each core and relevant microarchitecture telemetry at a granular level,” she said.
With Intel Thread Director, demanding applications like games or content creation software will be assigned to Performance Cores while lower-priority background tasks like email sync and network drive backup will run on the Efficient cores, according to Chabukswar.
But that intelligent workload scheduler can take things a step further. Chabukswar said if all the Performance cores are occupied and a new demanding thread appears, Intel Thread Director can communicate that to the operating system and move an existing thread on a Performance Core to an Efficient core, creating room for the new threaded that has higher performance requirements.
“This is where the dynamic nature of our innovation shines,” she said. “Nothing is static based on any software. Everything is dynamic, based on the current context of whatever is running on the system, all augmented by hardware telemetry.”