Intel Teases Purpose-Built 'Client 2.0' Processors With 'Mix And Match' Building Blocks

While many of Intel‘s new disclosures focused on products coming within the next year or two, the company also teased a more long-term change in how the company is designing next-generation chips for desktops and laptops in the future.

The company calls this new approach to client processor design “Client 2.0,” and it will focus on the creation of ”purpose-built” processors for different user types, like gamers, content creators and commercial users. This approach will be made possible by mixing and matching different silicon functions and IPs as building blocks—for things like graphics, compute and I/O—to optimize for different experiences, which is a major departure from Intel‘s traditional monolithic chip approach.

Brijesh Tripathi, vice president and chief technology officer for Intel‘s Client Computing Group, said Client 2.0 will allow a much quicker development time than it takes for monolithic and multi-die chips, which is made possible in part by the fact that the individual IP building blocks can be reused for different products at a much greater rate than its multi-die design methodology.

“Overall, Client 2.0 is about delivering winning products at an annual cadence,” he said.

Tripathi said the company plans to share more details of its Client 2.0 plans in the future.

“We‘ve been working on this for quite some time,” he said. ”In a world where customers demand extremely rich experiences for every use case, we have changed the way we think about our construction tools and methodology. Our purpose has changed from building monolithic general-purpose SoCs to building scalable, purpose-built devices to provide rich user experience.”

Intel Reveals 10nm SuperFin, 'Largest Single Intranode Enhancement'

Intel is taking a new approach to intranode enhancements for its products and getting rid of the plus sign that has been used for previous intranode enhancements like 14nm+++, the latest version of the company‘s 14-nanometer process used for processors like the Comet Lake H chips.

Headlining the new approach is Intel‘s first improvement of its 10nm process, called 10nm SuperFin, which the company said is the “largest single intranode enhancement in its history,” comparable to a full-node transition performancewise.

Ruth Brain, an Intel Fellow and director of interconnect technology and integration., said SuperFin is a redefining of the 3D FinFET transistors Intel introduced over a decade ago that have served as the foundation for the company‘s 14nm and 10nm products to date.

“The era of getting massive performance boost from simply shrinking transistor features is behind us,” she said.

10nm SuperFin, which serves as the basis for Intel‘s forthcoming Tiger Lake mobile processors, combines the company’s enhanced FinFET transistors with a new super metal-insulator-metal capacitor to drive performance and efficiency improvements in a variety of ways. 

The improvements include enhanced epitaxial growth of crystal structures and an additional gate pitch option to drive higher current through the transistor‘s channels. 10nm SuperFin also includes an improved gate process for higher channel mobility, a novel thin barrier to reduce electrical resistance by 30 percent and improve interconnect performance, as well as a five-fold increase in capacitance, which results in a reduction in voltage troop that “dramatically” improves performance.

“This is an industry-first technology that far exceeds the current capabilities of other manufacturers,” Brain said.